International Journal of Computer
Trends and Technology

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Volume 4 | Issue 10 | Year 2013 | Article Id. IJCTT-V4I10P138 | DOI : https://doi.org/10.14445/22312803/IJCTT-V4I10P138

Design And Implementation Of USART IP Soft Core Based On DMA Mode

Peddaraju Allam

Citation :

Peddaraju Allam, "Design And Implementation Of USART IP Soft Core Based On DMA Mode," International Journal of Computer Trends and Technology (IJCTT), vol. 4, no. 10, pp. 3580-3584, 2013. Crossref, https://doi.org/10.14445/22312803/IJCTT-V4I10P138

Abstract

A Universal synchronous Asynchronous Receiver/Transmitter is a type of "synchronous asynchronous receiver/transmitter", a piece of computer hardware that translates data between parallel and serial forms. The universal designation indicates that the data format and transmission speeds are configurable and that the actual electric signaling levels and typically is handled by a special driver circuit external to the USART. A USART is usually an individual (or part of an) integrated circuit used for serial communications over a computer or peripheral device serial port. USARTs are now commonly included in microcontrollers. A dual USART, or DUART, combines two USARTs into a single chip. Many modern ICs now come with a UART that can also communicate synchronously; these devices are called USARTs (universal synchronous/asynchronous receiver/transmitter).The USART IP hard core is poor at flexibility and transportability while USART IP soft core is only based on poll and interrupt mode at present which consumes so much time of CPU that the performance of embedded system is reduced greatly. USART (with reference of clock) IP soft core based on DMA mode is proposed and well elaborated using the characteristic of DMA. The IP core is AVALON bus-compatible with the control and arithmetic logic of entire IP core completed by a single FPGA chip so that it is very suited to NIOSII embedded system. Five main sub modules are well designed and the whole IP core is tested and verified in a simple NIOSII embedded hardware system. It turns out that USART IP soft core based on DMA mode can reduce elapsed time of CPU greatly in data transmission process so that the performance of NIOSII system can be improved and design requirement can be better met with less resources occupied, high speed, high flexibility and high transportability.

Keywords

NIOSII; USART; IP; DMA; AVALON bus

References

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