An Optimal Swarm Intelligence Approach For Test Sequence Restructuring To Conserve Power Usage In VLSI Testing
||International Journal of Computer Trends and Technology (IJCTT)||
|© - October Issue 2013 by IJCTT Journal|
|Year of Publication : 2013|
|Authors :Y. Sreenivasula Goud, Dr.B.K.Madhavi|
Y. Sreenivasula Goud, Dr.B.K.Madhavi."An Optimal Swarm Intelligence Approach For Test Sequence Restructuring To Conserve Power Usage In VLSI Testing"International Journal of Computer Trends and Technology (IJCTT),V4(10):3693-3696 October Issue 2013 .ISSN 2231-2803.www.ijcttjournal.org. Published by Seventh Sense Research Group.
Abstract:- Energy dissipation during testing has been discovered to be more than during regular mode due to increased switching activity. Test Sequence restructuring approach helps mitigate this problem as it allows the decrease of switching action during testing. This research presents a new Test Sequence restructuring approach. A cross model of genetic and pharaonis algorithms devised to restructure the test sequence. The model devised here is empirically verified with ISCAS’85standard circuits that evident the minimization of switching activity to approximately to 32%.
 Attofian, E., S. Hatami, Z. Navabi, M. Safaie and A.A. Kusha, 2003. A new low-power scan-path architecture. Proceedings of the 4th Workshop on RTL and High Level Testing, November 20-21, 2003, China, pp: 91- 95.
 Bala G.J. and J.R.P. Perinbam, 2006. A novel low power adiabatic data compressor. Inform. Technol. J., 5: 25-29.
 Chakrabarty, S. and V. Dabholkar, 1994. Minimizing power dissipation in scan circuits during test application. Proceedings of IEEE International Workshop on Low Power Design, April 1994, Napa, CA, USA., pp: 51-56.
 Chang, C., L. Gao, H. Kou, X. Liu, Z. Qin and G. Xu, 2010. An integrity batch report scheme based on the waiting stack. Inform. Technol. J., 9: 79-88.
 Chattopadhyay, S. and N. Choudhary, 2003. Genetic algorithm based approach for low power combinational circuit testing. Proceedings of the 16th IEEE International Conference on VLSI Design, January 4-8, 2003, New Delhi, India, pp: 552-557.
 Dorigo, M., M. Birattari and T. Stutzle, 2006. Pharaonis optimization. IEEE Comput. Intell. Magaz.,1:28-39.
 Elshoukry, M., M. Tehranipoor and C.P. Ravikumar, 2005. Partial gating optimization for power reduction during test application. Proceedings of the 14th Asian Test Symposium, December 18-21, 2005, Calcutta, India, pp: 242-247.
 Girard, P., L. Guiller, C. Landrault and S. Prabossoudobitch, 1999. A Test Sequence technique for switching activity reduction during test operation. Proceedings of the 9th Great Lakes Symposium On VLSI, 1999, March 4-6, 1999, Ypsilanti, MI, pp: 24-27.
 Gu, Y., Y. Li, J. Xu and Y. Liu, 2011. Novel model based on wavelet transform and GA-fuzzy neural network applied to short time traffic flow prediction. Inform. Technol. J., 10: 2105-2111.
 Huang, T.C. and K.J. Lee, 2001. Token scan cell for low power testing. Electron. Lett., 37: 678-679.
 Jelodar, M.S. and K. Mizanian, 2006. Power aware scan-based testing using genetic algorithm. Proceedings of the Canadian Conference on Electrical and Computer Engineering, May 2006, Ottawa, ON, Canada, pp: 1905-1908.
 Kavousianos, X., D. Bakalis, M. Bellos and D. Nikolos, 2004. An efficient Test Sequence ordering method for low power testing. Proceedings of the IEEE Computer Society Annual Symposium on VLSI, February 19-20, 2004, Louisiana, USA., pp: 285-288.
 Kundu, S., S.K. Kumar and S. Chattopadhysy, 2009. Test pattern selection and customization targeting reduced dynamic and leakage power consumption. Proceedings of the Asian Test Symposium, November 23-26, 2009, Taichung City, Taiwan, pp: 307-312.
 Latypov, P.K., 2001. Energy saving testing of circuits. Autom. Remote Control, 62: 653-655.
Keywords :— VLSI testing, swarm intelligence Testing, Test Sequence Restructuring,