Design and Analysis of 4- Bit Binary Synchronous Counter by Leakage Reduction Techniques

  IJCTT-book-cover
 
International Journal of Computer Trends and Technology (IJCTT)          
 
© 2017 by IJCTT Journal
Volume-50 Number-2
Year of Publication : 2017
Authors : Himal Pokhrel, Deepak Kumar, Anjali Sharma
  10.14445/22312803/IJCTT-V50P118

MLA

Himal Pokhrel, Deepak Kumar, Anjali Sharma "Design and Analysis of 4- Bit Binary Synchronous Counter by Leakage Reduction Techniques". International Journal of Computer Trends and Technology (IJCTT) V50(2):101-106, August 2017. ISSN:2231-2803. www.ijcttjournal.org. Published by Seventh Sense Research Group.

Abstract -
Counter is one of the fundamental and essential components used in most of the digital devices. Design of power efficient counter design has become essential for the researchers. In leakage dominant technologies, leakage current increases for traditional CMOS structures due to the reduction in threshold voltage. The increase in leakage current due to voltage scaling causes increase in static power dissipation. Various techniques have been implemented by the researchers to design counters which would consume the lowest power possible. In this paper, we have presented a design of 4 - bit binary synchronous counter using three different techniques namely CMOS technique, Sleepy transistor technique (STT) and Forced stack technique (FST). The circuit designing and parametric analysis has been carried out using microwind 3.1 and DSCH 3.1 software on 65nm technology. The height, width, surface area and power consumption in the case of all the three techniques have been measured at three different supply voltages i.e. 0.5V, 0.7V and 0.9V respectively. It is found that, the power consumed by FST counter and SST counter is much less as compared to power consumed by CMOS counter. The average power reduction is 44.9% in the case of sleepy transistor technique and the average power reduction is 70.1% in the case of FST as compared to CMOS counter. Although these techniques are power efficient as compared to CMOS technique but this is on the expense of larger surface area. Counter designed by these techniques can be useful where low power requirement will be primary concern.

References
1. Yogita Hiremath, Akalpita L. Kulkurani, J.S. Baligar “Design and implementation of synchronous 4-bit up counter using 180nm CMOS technology,” International Journal of Research in Engineering and Technology, Vol. 3, No.3, 2014.
2. Vinay Kumar Madasu, B Kedharnath “Leakage power reduction by using Sleep methods,” International journal of engineering and computer science, Vol. 2, No.9, 2013.
3. Rajani H.P and Shrimannarayan Kulkarni “Novel Sleep transistor technique low leakage power peripheral circuits,” International journal of VLSI design and communication system, Vol.3, No.4, 2012.
4. Kaushik Roy, Saibal Mukhopadhyay, Hamid Manmoodi-Meimand, “Leakage current mechanism and leakage reduction techniques in deep sub micrometer CMOS circuits,” Proceedings of the IEEE, Vol.91, 2003.
5. Shilpa Shrigiri, Yogina Bellad “Low power VLSI design approach for 16 bit binary counter to reduce power,” International journal of current engineering and technology.
6. Praween Sinha, Shreyaansh Shrivastava “ Design of a low power 4 bit binary counter using Enhancement type MOSFET, International journal of research and technology Vol.1, No. 8, 2012.
7. Calvignac Yvan , Cambonie Pierre “ 4-state binary counter; www.microwind.net
8. Sandeep Thakur, Rajesh Mehra, “Optimized Design and Simulation of Ring counter using 45nm technology,” International journal of engineering trends and technology Vol. 36, 2016.

Keywords
CMOS, DSCH, FST, Leakage Power, Microwind, Synchronous Counter.