Capacitance Scaling Based Low Power Comparator Design on 28nm FPGA

  IJCTT-book-cover
 
International Journal of Computer Trends and Technology (IJCTT)          
 
© 2016 by IJCTT Journal
Volume-42 Number-2
Year of Publication : 2016
Authors : Abhay Saxena, Swapnil Gaidhani, Anamika Pant, Chandrashekhar Patel
  10.14445/22312803/IJCTT-V42P112

MLA

Abhay Saxena, Swapnil Gaidhani, Anamika Pant, Chandrashekhar Patel  "Capacitance Scaling Based Low Power Comparator Design on 28nm FPGA". International Journal of Computer Trends and Technology (IJCTT) V42(2):72-76, December 2016. ISSN:2231-2803. www.ijcttjournal.org. Published by Seventh Sense Research Group.

Abstract -
Reducing the power consumption is the main concern in green computing. So here we used capacitance scaling technique on comparator for optimizing the power. We worked with I/O Power & Leakage Power because Clock Power & Signal Power are independent of capacitance scaling. In our work we have scaled down the capacitance from 512pF to 32pF at various fixed frequency. At 1GHz when we scale down the capacitance from 512pF to 32pF then we got 91.26% reduction in total I/O power dissipation. At 10 GHz when we scale down the capacitance from 512pF to 32pF then we got 91.36% reduction in total I/O power dissipation. At 20 GHz when we scale down the capacitance from 512pF to 32pF then we got 91.364% reduction in total I/O power dissipation. At 30 GHz when we scale down the capacitance from 512pF to 32pF then we got 91.3624% reduction in total I/O power dissipation. At 40GHz when we scale down the capacitance from 512pF to 32pF then we got 91.36277% reduction in total I/O power dissipation. This design is implemented on 28 nm Artix7 FPGA.

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Keywords
Capacitance Scaling, Low Power, Comparator, 28nm, FPGA, Computer Architecture.