Design and Analysis of Modified Fast Compressors for MAC Unit

  IJCTT-book-cover
 
International Journal of Computer Trends and Technology (IJCTT)          
 
© 2016 by IJCTT Journal
Volume-36 Number-4
Year of Publication : 2016
Authors : Anusree T U, Bonifus P L
  10.14445/22312803/IJCTT-V36P137

MLA

Anusree T U, Bonifus P L "Design and Analysis of Modified Fast Compressors for MAC Unit". International Journal of Computer Trends and Technology (IJCTT) V36(4):213-218 June 2016. ISSN:2231-2803. www.ijcttjournal.org. Published by Seventh Sense Research Group.

Abstract -
Multiplication and addition are the basic arithmetic operations which are important in several microprocessors and digital signal processing (DSP) applications. As the demand for high speed multipliers is continuously increasing, the studies related to the field of multipliers and adders are endless and still significant. Compressors can be used with the aim of reducing the power dissipation of multipliers without compromising their speed performance in which only multiplexer and basic gates are used. In this work, different topologies of 4:2 and 5:2 compressors are compared in terms of power delay product and number of transistors. Compressor topologies are simulated in 90nm Technology using Cadence Virtuoso schematic editor at 700mV power supply. The improved design can be used in multipliers with minimum delay than conventional ones which can be used in MAC units applied for DSP applications.

References
[1] Ming Bo Lin, Introduction to VLSI Systems, CRC Press. November, 2011, pp .256-300.
[2] O. Kwon, K. Nowka and E. E. Swartzlander, A 16-Bit by 16-Bit MAC Design Using Fast 5:3 Compressor Cells, The Journal of VLSI Signal Processing,2002, vol. 31.
[3] Amir Momeni and Paolo Montuschi, ―Design and Analysis of Approximate Compressors for Multiplication, IEEE Transactions on Computers, 2015. Vol. 64, No. 4.
[4] A. Naja, S. Timarchi and A. Naja, ―High-speed Energy efficient 5:2 Compressor, Proceedings of MIPRO. Opatija, Croatia, 2014.
[5] S. Veeramachaneni, K. M. Krishna, L. Avinash, S. R. Puppala and M. B. Srinivas, ―Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors, International Conference on VLSI Design, 2007.
[6] Shanthala S, Cyril Prasanna Raj and Dr. S Y Kulkarni, ―Design and VLSI Implementation of Pipelined Multiply Accumulate Unit, Second International Conference On Emerging Trends in Engineering Technology, ICETET, 2009.
[7] Amir Naja, Ardalan Naja and Sattar Mirzakuchaki, ―Lowpower and High performance 5:2 Compressors, 22nd Iranian Conference on Electrical Engineering, 2014, May pp. 20-22.
[8] Teffi Francis, Tera Joseph and Jobin K Antony, ―Modified MAC Unit for Low Power High Speed DSP Application Using Multiplier with Bypassing Technique and Optimized Adders, IEEE-31661, 4th ICCCNT, 2013.
[9] Geoffknage homepage on carry save addition. (2010) [Online]. Available: http://www.geo_knagge.com/fyp/carrysave.shtml
[10] K.N.V.S Vijaya Lakshmi and D.R.Sandeep, ―LowPower32-Bit DADDA Multiplier, International Journal of Computer Trends and Technology (IJCTT), volume 17, 2014, November.
[11] Chandra.K and Kumar.P, ―Optimization of RSA Processors Using Multiplier, International Journal of Computer Trends and Technology (IJCTT), volume 4, Issue5–May 2013, Page 1089

Keywords
4:2 compressor, 5:2 compressor, Pass transistor logic, MAC unit.