Integer N Frequency Synthesizer using Phase Lock Loop

  IJCTT-book-cover
 
International Journal of Computer Trends and Technology (IJCTT)          
 
© 2016 by IJCTT Journal
Volume-32 Number-1
Year of Publication : 2016
Authors : Pallavi Patil, Virendra K. Verma
  10.14445/22312803/IJCTT-V32P102

MLA

Pallavi Patil, Virendra K. Verma "Integer N Frequency Synthesizer using Phase Lock Loop". International Journal of Computer Trends and Technology (IJCTT) V32(1):8-13, February 2016. ISSN:2231-2803. www.ijcttjournal.org. Published by Seventh Sense Research Group.

Abstract -
A new architecture and simulation of an integer n frequency synthesizer using PLL for RF application has been illustrated in this paper. This design consists of low power phase frequency detector, low jitter charge pump, ring oscillator based VCO, passive loop filter and 8 bit frequency divider using 250nm technology. This presents the simplest way to design and simulate integer n frequency synthesizer and lock the PLL. The design and analysis of PLL is done on simulation EDA TANNER TOOL 13.0.The main benefit of using PLL technique in Frequency Synthesizer is that it can generate frequencies of 100- 200MHz comparable to the accuracy of a crystal oscillator. This paper gives a brief introduction to the basics of Phase Locked loops.

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Keywords
Phase locked loop, Phase frequency detector, Charge pump, Loop filter, Voltage controlled oscillator, Frequency divider.