International Journal of Computer
Trends and Technology

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Volume 6 | Number 1 | Year 2013 | Article Id. IJCTT-V6N1P102 | DOI : https://doi.org/10.14445/22312803/IJCTT-V6N1P102

FPGA Implementation of Lifting DWT based LSB Steganography using Micro Blaze Processor

B.Vasantha Lakshmi, B.Vidheya Raju

Citation :

B.Vasantha Lakshmi, B.Vidheya Raju, "FPGA Implementation of Lifting DWT based LSB Steganography using Micro Blaze Processor," International Journal of Computer Trends and Technology (IJCTT), vol. 6, no. 1, pp. 6-14, 2013. Crossref, https://doi.org/10.14445/22312803/IJCTT-V6N1P102

Abstract

We present an information hiding technique that utilizes lifting schemes to effectively hide information in images. A successful information hiding should result in the extraction of the hidden data from the image with high degree of data integrity. Current trends favor using digital image files as the cover file to hide another digital file that contains the secret message or information. The Least Significant Bit (LSB) embedding technique suggests that data can be hidden in the least significant bits of the cover image and the human eye would be unable to notice the hidden information in the cover file. This paper explains the LSB Embedding technique with lifting based DWT schemes by using Micro blaze Processor implemented in a FPGA using System C coding.

Keywords

Steganography, DWT, LSB, Micro Blaze, FPGA.

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