International Journal of Computer
Trends and Technology

Research Article | Open Access | Download PDF

Volume 5 | Number 2 | Year 2013 | Article Id. IJCTT-V5N4P134 | DOI : https://doi.org/10.14445/22312803/IJCTT-V5N4P134

Block Floating Point Implementations for DSP Computations in Reconfigurable Computing

Georgina Binoy Joseph

Citation :

Georgina Binoy Joseph, "Block Floating Point Implementations for DSP Computations in Reconfigurable Computing," International Journal of Computer Trends and Technology (IJCTT), vol. 5, no. 2, pp. 179-182, 2013. Crossref, https://doi.org/10.14445/22312803/IJCTT-V5N4P134

Abstract

The IEEE-754 standard prescribes standards for 32 bit single precision and 64 bit double precision formats. For DSP applications that require a large dynamic range floating point implementations are more suitable than fixed point representation. This advantage is offset by the cost of the implementation. The block floating point (BFP) concept combines the precision and cost effectiveness of fixed point representations with the increased dynamic range of floating point representations. BFP is of particular importance in FPGA implementations of DSP algorithms. In this paper the embedded multipliers available in present day reconfigurable devices facilitate the implementation of efficient BFP architectures for DSP applications.

Keywords

block floating point; dynamic range; fixed point; reconfigurable computing; DSP applications.

References

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