International Journal of Computer
Trends and Technology

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Volume 4 | Issue 9 | Year 2013 | Article Id. IJCTT-V4I9P154 | DOI : https://doi.org/10.14445/22312803/IJCTT-V4I9P154

An Optimization Technique for CRC Generation

K.V.Krishna

Citation :

K.V.Krishna, "An Optimization Technique for CRC Generation," International Journal of Computer Trends and Technology (IJCTT), vol. 4, no. 9, pp. 3260-3265, 2013. Crossref, https://doi.org/10.14445/22312803/IJCTT-V4I9P154

Abstract

In networking environments, the cyclic redundancy check (CRC) is widely utilized to determine whether errors have been introduced during transmissions over physical links. In this paper, we present a fast cyclic redundancy check (CRC) algorithm that performs CRC computation for an arbitrary length of message in parallel. This paper proposes 64 bits parallel CRC architecture based on F matrix with order of generator polynomial is 32 and showed CRC-64 is having less latency and high throughput compared to CRC-32 parallel architecture through Xilinx Simulator.

Keywords

CRC, lookup table, Fast update

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