International Journal of Computer
Trends and Technology

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Volume 4 | Issue 5 | Year 2013 | Article Id. IJCTT-V4I5P46 | DOI : https://doi.org/10.14445/22312803/IJCTT-V4I5P46

Modification of Instruction Set Architecture in a UTeMRISCII Processor

Ahmad Jamal Salim, Nur Raihana Samsudin, Sani Irwan Md Salim , Soo Yew Guan

Citation :

Ahmad Jamal Salim, Nur Raihana Samsudin, Sani Irwan Md Salim , Soo Yew Guan, "Modification of Instruction Set Architecture in a UTeMRISCII Processor," International Journal of Computer Trends and Technology (IJCTT), vol. 4, no. 5, pp. 1196-1201, 2013. Crossref, https://doi.org/10.14445/22312803/IJCTT-V4I5P46

Abstract

The development of application specific instruction set processor (ASIP) is a methodology in designing the processor system. The designing of processor system is focused on the internal architecture of the processor. By using the ASIP design, it can offer the optimum performance and also the flexibility in a processor architecture, but with limited application. However, by implementing the processor on Field Programmable Gate Array (FPGA), it could further extend the opportunity to reconfigure the architecture instantly. Therefore, this paper is about the implementation of the modification of a 16-bit wide instruction set for a simple 8-bit soft-core RISC processor called UTeMRISCII. The purpose of the project is to improve the ability of the processor by adding a new instruction set that can be able to perform basic digital signal processing (DSP) algorithm. For verification, a multiply-accumulate (MAC) instruction is created as the new customized instruction. The modification of the instruction set architecture is achieved by using Hardware Description Language (HDL) implementation. To validate the operation of new customized instruction in the software platform, the CPUSim software is used as the simulator to observe the output. Meanwhile, in the hardware platform, the new customized instruction is translated into processor design and verified using the Xilinx ISE software. The Xilinx Virtex-6 board is used to implement the processor. The simulation and hardware synthesis results proved that the new MAC instruction implementation performed correctly and produces correct outputs during the processor execution.

Keywords

ASIP; modification instruction set; Multiply-accumulate.

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