International Journal of Computer
Trends and Technology

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Volume 4 | Issue 4 | Year 2013 | Article Id. IJCTT-V4I4P162 | DOI : https://doi.org/10.14445/22312803/IJCTT-V4I4P162

Spartan 3E Synthesizable FPGA Based Floating-Point Arithmetic Unit

Yedukondala Rao Veeranki, R. Nakkeeran

Citation :

Yedukondala Rao Veeranki, R. Nakkeeran, "Spartan 3E Synthesizable FPGA Based Floating-Point Arithmetic Unit," International Journal of Computer Trends and Technology (IJCTT), vol. 4, no. 4, pp. 751-755, 2013. Crossref, https://doi.org/10.14445/22312803/ IJCTT-V4I4P162

Abstract

Floating point operations are hard to implement on Field Programmable Gate Arrays (FPGA) because of the complexity of algorithms is more. Then again, many scientific applications require floating point arithmetic because of high accuracy in their calculations. Therefore, an attempt is made to explore FPGA implementations in Institute of Electrical and Electronics Engineers (IEEE) -754 standard floating-point numbers. Many algorithms depend on floating point arithmetic because floating point representation supports huge range. In this paper an efficient implementation of an IEEE 754 single precision floating point arithmetic unit is designed in Xilinx SPARTAN 3E FPGA. VHDL environment is performed for floating point arithmetic unit design using pipelining, which provides high performance. Pipelining is used to execute multiple instructions simultaneously. In top-down design approach, four arithmetic modules, addition/ subtraction, multiplication and division are combined to form a floating point arithmetic unit. Synthesis and simulation results are obtained by using Xilinx13.1i platform.

Keywords

ALU - Arithmetic Logic Unit; Top-Down design; floating point; FPGA; Pipelined Architecture.

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