International Journal of Computer
Trends and Technology

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Volume 4 | Issue 4 | Year 2013 | Article Id. IJCTT-V4I4P125 | DOI : https://doi.org/10.14445/22312803/IJCTT-V4I4P125

Power Reduction and Speed Augmentation in LFSR for Improved Sequence Generation Using Transistor Stacking Method

Vikas Sahu, Mr. Pradeep Kumar

Citation :

Vikas Sahu, Mr. Pradeep Kumar, "Power Reduction and Speed Augmentation in LFSR for Improved Sequence Generation Using Transistor Stacking Method," International Journal of Computer Trends and Technology (IJCTT), vol. 4, no. 4, pp. 560-566, 2013. Crossref, https://doi.org/10.14445/22312803/IJCTT-V4I4P125

Abstract

In many electronics circuit Linear Feedback Shift Register (LFSR) used for generating sequences. So for high performance applications LFSR should have to generate efficient sequences. There are so many methods of generating very efficient sequences. The demand and popularity of portable LFSR is driving designers to strive for small silicon area, higher speeds, low power dissipation and reliability. Compared to static LFSR, dynamic LFSR offers good performance. Wide fan-in logic such as domino LFSR is used in high-performance applications. Dynamic domino LFSRs are widely used in modern digital VLSI circuits. These dynamic LFSRs are often favored in high performance designs because of the speed advantage offered over static LFSR circuits. This paper compares different types of LFSR on the basis of performance parameter such as power consumption, propagation delay and leakage current at 65 nm, 45 nm, 32 nm and 25nm technologies for high performance LFSR design. The techniques are compared by performing detailed transistor simulations on benchmark circuits using Microwind 3 and DSCH 3 CMOS layout CAD tools.

Keywords

LFSR, Leakage current, Power dissipation, Propagation Delay and VLSI.

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