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Volume 4 | Issue 2 | Year 2013 | Article Id. IJCTT-V4I2P116 | DOI : https://doi.org/10.14445/22312803/IJCTT-V4I2P116
High performance Level Conversion Flip Flop for Dual Supply Systems
K.Padma Priya
Citation :
K.Padma Priya, "High performance Level Conversion Flip Flop for Dual Supply Systems," International Journal of Computer Trends and Technology (IJCTT), vol. 4, no. 2, pp. 132-134, 2013. Crossref, https://doi.org/10.14445/22312803/IJCTT-V4I2P116
Abstract
In this paper high performance level conversion flip flop has been designed. The circuit has been designed by reducing internal switching activity and glitches. The new FF has introduced with conditional discharged to reduce the power consumption. This Conditional Discharge Flip Flop (CDFF) not only reduces the internal switching activities, but also generates less glitches at the output, while maintaining by maintaining minimum delay between D-to-Q.
Keywords
Dual supply, level conversion, low power, conditional discharge.
References
[1] L. Benini, E. Macii, and G. De Micheli, “Designing low power circuits: Practical recipes,” IEEE Circuit Syst. Mag., vol. 1, no. 1, pp. 6–25,2001.
[2] S. Kulkarni and D. Sylvester, “High performance level conversion for dual VDD design,” IEEE Trans. Very Large Scale Integr. VLSI. Syst., vol. 12, no. 9, pp. 926–936, Sep. 2004.
[3] R. Krishnamurthy, S. Hsu, M. Anders, and B. Bloechel, “Dual supply voltage clocking for 5 G, 130 nm integer execution core,” in Proc. IEEE Very Large Scale Integr. (VLSI) Symp., 2002, pp. 128–129.
[4] M. Bai and D. Sylvester, “Analysis and design of level-converting flip- flops for dual-Vdd/Vth integrated circuits,” in Proc. IEEE Int. Symp. System-on-Chip, 2003, pp. 151–154.
[5] H. Mahmoodi-Meimand and K. Roy, “Self-precharging flip-flop (SPFF): a new level converting flip-flop,” in Proc. Eur. Solid-State Circuits Conf., Sep. 2002, pp. 407–410.
[6] P. Zhao, G. P. Kumar, and M. Bayoumi, “Contention reduced conditional discharge flip-flops for level conversion in CVS systems,” in Proc. IEEE Int. Symp. Circuits Syst., Vancouver, BC, Canada, May 23–26, 2004, pp. 669–672.
[7] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Cir- cuits. Englewood Cliffs, NJ: Prentice-Hall, 2003.
[8] P. Zhao, T. Darwish, and M. Bayoumi, “High-performance and low- power conditional discharge flip-flop,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 5, pp. 477–484, May 2004.
[9] P. Zhao, J. McNeely, P. Golconda, M. A. Bayoumi, W. D. Kuang, and B. Barcenas, “Low power clock branch sharing double-edge triggered flipflop,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 3, pp. 338–345, Mar. 2007. [10] D. A. Hodges, H. G. Jackson, and R. A. Saleh, Analysis and Design of Digital Integrated Circuits, 3rd ed. New York: McGraw-Hill, 2004.
[11] V. Stojanovic and V. Oklobdzija, “Comparative analysis of master-slave latches and flip-flops for high-performance and low power system,” IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536–548, Apr. 1999.
[12] B. Kong, S. Kim, and Y. Jun, “Conditional-capture flip-flop for statis- tical power reduction,” IEEE J. Solid-State Circuits, vol. 36, no. 8, pp.1263–1271, Aug. 2001.
[13] B.Jason, G.Pradeep,V.Soujanya,A.Bayoumi,L.Downey.”Low – power clocked –pseudo-NMOS Flip-Flop for level conversion in dual supply systems”,in proc. IEEE tran.very large scale integ.sys, vol. 17, no. 9, pp. 1196–1202, 2009.
[14] S. H. Kulkarni and D. Sylvester, “Fast and Energy-Efficient Asynchronous Level Converters for Multi-VDD Design,” in Proceedings of the International Symposium on Low Power Electronics and Design, 2004, pp. 200-2005.
[15] F. Ishihara and F. Sheikh, “Level Conversion for Dual-Supply Systems,” IEEE Transactions on Very Large Scale Integration Systems, Vol.12, Issue 2, February 2004, pp. 185-195. [16] K. Usami and M. Igarashi, “Low-Power Design Methodology and Applications Utilizing Dual Supply Voltages,” in Asia South Pacific Design Automation Conference, 2000, pp.123-128.
[16] N. Weste and D. Harris, CMOS VLSI Design. Reading, MA: AddisonWesley, 2004.