International Journal of Computer
Trends and Technology

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Volume 3 | Issue 4 | Year 2012 | Article Id. IJCTT-V3I4P118 | DOI : https://doi.org/10.14445/22312803/IJCTT-V3I4P118

A New Reduced Clock Power Flip-flop for Future SOC Applications

T.Kavitha , Dr.V.Sumalatha

Citation :

T.Kavitha , Dr.V.Sumalatha, "A New Reduced Clock Power Flip-flop for Future SOC Applications," International Journal of Computer Trends and Technology (IJCTT), vol. 3, no. 4, pp. 491-495, 2012. Crossref, https://doi.org/10.14445/22312803/IJCTT-V3I4P118

Abstract

In this paper a novel technique is proposed based on the comparison between Conventional Conditional Data Mapping Flip-flop and Clock Pair Shared D flip flop(CPSFF) here we are checking the working of CDMFF and the conventional D Flip-flop. Due to the immense growth in nanometer technology the SOC is became the future concept of the modern electronics the number of clock transistors are also considerably increased. In this paper we propose a new system which will considerably reduce the number of transistor which will lead to the reduction in clocking power which will improve the overall power consumption.Our proposed which is designed using Pass Transistor Logic (LCPTFF) Low Power Clocked Pass Transistor Flip-Flop system is showing much better output than all other designs as mentioned in the tabulation.The simulations are done using Microwind& DSCH analysis software tools and the result between all those types are listed below.

Keywords

Flip-flop, Low Power Clocking System, Sequential Elements, DSCH, Microwind

References

[1]. J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits. Englewood Cliffs, NJ: Prentice-Hall, 2003.
[2]. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, “A 1-V high-speed MTCMOS circuit scheme for power-down application circuits,” IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 861–869, Jun. 1997.
[3]. T. Sakurai, “Low –power CMOS design through Vth control and lowswing circuits,” in Proc. ISLPED, 1997, pp. 1–6.
[4]. C. K. Teh, M. Hamada, T. Fujita, H. Hara, N. Ikumi, and Y. Oowaki, “Conditional data mapping flip-flops for low-power and high-performance systems,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 12, pp. 1379–1383, Dec. 2006.
[5]. D. A. Hodges, H. G. Jackson, and R. A. Saleh, Analysis and Design of Digital Integrated Circuits, 3rd ed. New York: McGraw-Hill, 2004.
[6]. V. G. Oklobdzija, “Clocking in multi-GHz environment,” in Proc. 23rd IEEE Int. Conf. Microelectron., 2002, vol. 2, pp. 561–568.
[7] J. Tschanz, S. Narendra, Z. P. Chen, S. Borkar,M. Sachdev, and V. De, “Comparative delay and energy of single edge-
[8] triggered & dual edge triggered pulsed flip-flops for highperformance microprocessors,” in Proc. ISPLED, Huntington Beach, CA, Aug. 2001, pp. 207–212. 
[9] Beach, CA, Aug. 2001, pp. 207–212. P. Zhao, J. McNeely, P. Golconda, M. A. Bayoumi, W. D. Kuang, and B. Barcenas, “Low power clock branch sharing double-edge triggered flip-flop,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 3, pp. 338–345, Mar. 2007. 
[10]  C. L. Kim and S. Kang, “A low-swing clock double edgetriggered flip-flop,” IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 648–652, May 2002. 
[11]  P. Zhao, J. McNeely, S.Venigalla, G. P. Kumar,M. Bayoumi, N.Wang, and L. Downey, “Clocked-pseudo-NMOS flip-flops for level conversion in dual supply systems,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., to be published.
[12]   H. Partovi, R. Burd, U. Salim, F.Weber, L. DiGregorio, and D. Draper, “Flow-through latch and edge-triggered flip-flop hybrid elements,” in ISSCC Dig., Feb. 1996, pp. 138–139
[13] F. Klass, C. Amir, A. Das, K. Aingaran, C. Truong, R.Wang, A. Mehta,  Heald, and G. Yee, “Semi-dynamic and dynamic flipflops with embedded logic,” in Symp. VLSI Circuits, Dig. Tech. Papers, Jun. 1998, pp. 108–109. 
[14] D. Markovic, B. Nikolic, and R. Brodersen, “Analysis and design of low-energy flip-flops,” in Proc. Int. Symp. Low Power Electron. Des.,Huntington Beach, CA, Aug. 2001, pp. 52–55. 
[15] J. Tschanz, Y. Ye, L. Wei, V. Govindarajulu, N. Borkar, S. Burns, T. Karnik, S. Borkar, and V. De, “Design optimizations of a high performance microprocessor using combinations of dual-Vtallocation and transistor sizing,” in IEEE Symp. VLSI Circuits, Dig. Tech. Papers, Jun. 2002, pp. 218–219. 
[16] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits. Englewood Cliffs, NJ: Prentice-Hall, 2003.
[17] Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, “A 1-V high-speed MTCMOS circuit scheme for power-down application circuits,” IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 861–869, Jun. 1997.
[18] Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, “A 1-V high-speed MTCMOS circuit scheme for power-down application circuits,” IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 861–869, Jun. 1997.
[19] C. K. Teh, M. Hamada, T. Fujita, H. Hara, N. Ikumi, and Y. Oowaki, “Conditional data mapping flip-flops for low-power and high-performance systems,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 12, pp. 1379–1383, Dec. 2006. 
[20] D. A. Hodges, H. G. Jackson, and R. A. Saleh, Analysis and Design of Digital Integrated Circuits, 3rd ed. New York: McGraw-Hill, 2004. 
[21] V. G. Oklobdzija, “Clocking in multi-GHz environment,” in Proc. 23rd IEEE Int. Conf. Microelectron., 2002, vol. 2, pp. 561–568.