International Journal of Computer
Trends and Technology

Research Article | Open Access | Download PDF

Volume 1 | Issue 3 | Year 2011 | Article Id. IJCTT-V1I3P105 | DOI : https://doi.org/10.14445/22312803/IJCTT-V1I3P105

Design and Analysis of On-Chip Router for Network On Chip

Ms. A.S. Kale,Prof. M.A.Gaikwad

Citation :

Ms. A.S. Kale,Prof. M.A.Gaikwad, "Design and Analysis of On-Chip Router for Network On Chip," International Journal of Computer Trends and Technology (IJCTT), vol. 1, no. 3, pp. 264-268, 2011. Crossref, https://doi.org/10.14445/22312803/ IJCTT-V1I3P105

Abstract

Continuous scaling of CMOS technology makes it possible to integrate a large number of heterogeneous devices that need to communicate efficiently on a single chip. For this efficient routers are needed to takes place communication between these devices. This paper gives the design of on-chip routers based on optimizing power consumption and chip area. Proposed architecture of on-chip router in this paper give the results in which power consumption is reduced and silicon area is also minimize.

Keywords

Arbiter, Network on chip (NOC), Router.

References

[1] W. 1. Dally and B. Towles, Route Packets, Not Wires: On-Chip Interconnection Networks, In Proceedings of the 38th Design Automation Conference, p.684 (2001)
[2] L. Benini and D. Micheli, Networks on Chips: A New SoC Paradigm, IEEE Computer, 35, p.70 (2002)
[3]Khalid Latif, Tiberiu Seceleanu, Hannu Tenhunen, Power and Area Efficient Design of Network-on-Chip Router Through Utilization of Idle Buffers
[4]Cheng Liu·, Liyi Xiao, Fangfa Fu, Design and Analysis of OnChip Router
[5]Eung S. Shin, Vincent J. Mooney III and George F. Riley, Round-robin Arbiter Design and Generation