International Journal of Computer
Trends and Technology

Research Article | Open Access | Download PDF

Volume 2 | Issue 1 | Year 2011 | Article Id. IJCTT-V2I1P115 | DOI : https://doi.org/10.14445/22312803/IJCTT-V2I1P115

Low Power testing by don’t care bit filling technique

Chetan Sharma

Citation :

Chetan Sharma, "Low Power testing by don’t care bit filling technique," International Journal of Computer Trends and Technology (IJCTT), vol. 2, no. 1, pp. 314-316, 2011. Crossref, https://doi.org/10.14445/22312803/IJCTT-V2I1P115

Abstract

Test power is major issue of recent scenario of VLSI testing. There are many test pattern generation techniques for testing of combinational circuits with different tradeoffs. The don’t care bit filling method can be used for effective test data compression as well as reduction in scan power. This paper gives a new advancement in automatic test pattern generation method by feeling don’t care bit of the test vector to optimize the switching activities. Finally this concept produces low power testing.

Keywords

ATPG test vector generation, Huffman code, Parity bit generation, Switching activity.

References

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