Design and Analysis of Power Efficient PTL Half Subtractor Using 120nm Technology

International Journal of Computer Trends and Technology (IJCTT)          
© 2014 by IJCTT Journal
Volume-7 Number-4                          
Year of Publication : 2014
Authors : Pranshu Sharma , Anjali Sharma
DOI :  10.14445/22312803/IJCTT-V7P153


      Pranshu Sharma , Anjali Sharma. Article: Design and Analysis of Power Efficient PTL Half Subtractor Using 120nm Technology. International Journal of Computer Trends and Technology (IJCTT) 7(4):207-213, January 2014. Published by Seventh Sense Research Group.

      In the designing of any VLSI System, arithmetic circuits play a vital role, subtractor circuit is one among them. In this paper a Power efficient Half-Subtractor has been designed using the PTL technique. Subtractor circuit using this technique consumes less power in comparison to the CMOS and TG techniques. The proposed Half-Subtractor circuit using the PTL technique consists of 6 NMOS and 4 PMOS. The proposed PTL Half-Subtractor is designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. The power estimation and simulation of layout has been done for the proposed PTL half-Subtractor design. Power comparison on BSIM-4 and LEVEL-3 has been performed with respect to the supply voltage on 120nm. Results show that area consumed by the proposed PTL Half-Subtractor is 147.8µm2 on 120nm technology. At 1V power supply the proposed PTL Half-Subtractor consumes 3.353µW power on BSIM-4 and 3.546µW power on LEVEL-3. The proposed circuit has also been compared with other Subtractor designs using CMOS and TG logics, and the proposed design has been proven power efficient as compared to design by other logics.

[1] Reto Zimmermann and Wolfgang Fichtner , “Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic”, IEEE Journal of Solid-State Circuits, Vol. 32, No. 7 , pp.1-12
[2] N. Weste and K. Eshraghian, “Principles of CMOS VLSI Design: A System Perspective Reading”, Pearson Education, Addison–Wesley, pp. 145-331.
[3] Sung-Mo Kang, Yusuf Leblebici, “CMOS Digital Integrated Circuits: Analysis and Design”, pp. 218-307.
[4] Anil K. Maini, “Digital Electronics Principles and Integrated Circuits “, pp. 209-211.
[5] Tanvi Sood, Rajesh Mehra ,” Design a Low Power Half-Subtractor Using .90µm CMOS Technology”, IOSR Journal of VLSI and Signal Processing , Vol.2, No.3 , pp. 51-56.
[6] Devendra Kumar Gautam, Dr. S R P Sinha, Er. Yogesh Kumar Verma, “ Design a Low Power Half-Subtractor Using AVL Technique Based on 65nm CMOS Technology”, International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Vol. 2, No.11,pp. 2891-2897.
[7] Anjali Sharma, Richa Singh, Pankaj Kajla “Area Efficient 1-Bit Comparator Design by using Hybridized Full Adder Module based on PTL and GDI Logic,” International Journal of Computer Applications, Vol.82, No. 10, pp. 5-13.
[8] Jin-Fa-Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, and Cheng-Che Ho, “A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design,” IEEE Transaction on Circuits and Systems I, Vol. 54, No. 5, pp. 1050-1059.
[9] Morgenshtein, A.; Fish, A.; Wagner, I.A., “Gate-diffusion input (GDI): A Power Efficient Method for Digital Combinational circuits,” IEEE Transaction on Very Large Scale Integration Systems, Vol. 10 , No. 5, pp. 566 - 581, 2002.
[10] Microwind and DSCH version 3.1, User’s Manual, Copyright 1997-2007, Microwind INSA France, pp. 97-103.

Keywords-AVLG, AVLS, BSIM, CMOS, DSCH, Gate Diffusion Input, PTL, Transmission Gate