Adiabatic Logic For Low Power Application Using Design 180nm Technology
| ||International Journal of Computer Trends and Technology (IJCTT)|| |
|© - April Issue 2013 by IJCTT Journal|
|Volume-4 Issue-4 |
|Year of Publication : 2013|
|Authors : Nikunj R Patel, Sarman K Hadia|
Nikunj R Patel, Sarman K Hadia "Adiabatic Logic For Low Power Application Using Design 180nm Technology"International Journal of Computer Trends and Technology (IJCTT),V4(4):800-804 April Issue 2013 .ISSN 2231-2803.www.ijcttjournal.org. Published by Seventh Sense Research Group.
Abstract: -Adiabatic circuits and standard CMOS logic are widely employed in Low power VLSI chips to achieve high system performance. The power saving of adiabatic circuit can reach more than 90% compared to conventional static CMOS logic. The clocking schemes and signal waveforms of adiabatic are different from those of standard CMOS circuits. This thesis work demonstrates the low power dissipation of Adiabatic Logic by presenting the results of designing various design/ cell units employing Adiabatic Logic circuit techniques( an inverter, a two-input NAND gate, a two-input NOR gate, a two-input XOR gate, a two-to-one multiplexer and a one-bit carry Adder) This paper also investigates the different power delay product over the wide range of supply voltages. Power dissipation has been calculated for different values.
 A. P. CHANDRAKASAN, S. SHENG, AND R. W. BRODERSEN, “Low Power CMOS Digital Design,” IEEE Journal of Solid-state Circuits, Vol. 27, No. 04, pp. 473-484, April 1999
 W. C. ATHAS, L. SVENSSON, J. KOLLER, N. TZARTZANIS, AND Y. CHOU, “Low Power Digital Systems based on Adiabatic Switching Principles,” IEEE Trans. on VLSI Systems, Vol. 2, No. 4, pp. 398-406, Dec. 1994
 W. C. ATHAS, J. G. KOLLER, L. SVENSSON, “An Energy- Efficient CMOS Line Driver using Adiabatic Switching,” Fourth Great Lakes symposium on VLSI, California, March 2005
 N. Anuar, Y. Takahashi and T. Sekine, “Two phase clocked adiabatic static CMOS logic and its Logic Family,” Joural of Semiconductor Technology & Science. Vol.10 No.1, Mar. 2010.
M. Pedram. Power minimization in IC Design: Principles of Applications, ACM Transactions on Design automation of Electronic System, 1(1) Jan 1996, pp 53-56.
 A. Blotti, S. Di Pascoli and R. Saletti: “Simple model for positive feedback adiabatic logic power consumption estimation”. Electronics Letters, Vol. 36, No. 2, Jan. 2000.
A. Blotti, M. Castellucci, and R. Saletti. Designing Carry Lookahead Adders with an Adiabatic Logic, Standard-cell Library, In Proc. 12th Int. Workshop PATMOS, Seville, Spain, Sept. 2002.
 Keivan Navi and Omid Kavehei, “ Low power and high performance 1- bit CMOS full adder cell ” in Journal of Computer, VOL. 3, No.2, FEB 2008.
 SUNG-MO KANG AND YUSUF LEBLEBICI, CMOS Digital Integrated Circuits - Analysis and Design, McGraw-Hill, 2003.
 WU, A., and NG, C.K.: ”High performance low power low voltage adder ”, Elec- tron. Letl.,1997, 33, (8).
 A. Vetuli, S. Di Pascoli and L. M. Reyneri: “Positive feedback in adiabatic logic”. Electronics Letters, Vol. 32, No. 20, Sep. 1996.
 Praveer Saxena ,Prof. Dinesh Chandra, Sampath Kumar V “AN ADIABATIC APPROACH FOR LOW POWER FULL ADDER DESIGN” International Journal on Computer Science and Engineering (IJCSE) Vol. 3 No. 9 september 2011.
Keywords — Low Power, Adiabatic logic, Energy dissipation, Positive Feedback Adiabatic Logic, Energy recovery