Spartan 3E Synthesizable FPGA Based Floating-Point Arithmetic Unit
| ||International Journal of Computer Trends and Technology (IJCTT)|| |
|© - April Issue 2013 by IJCTT Journal|
|Volume-4 Issue-4 |
|Year of Publication : 2013|
|Authors : Yedukondala Rao Veeranki, R. Nakkeeran|
Yedukondala Rao Veeranki, R. Nakkeeran "Spartan 3E Synthesizable FPGA Based Floating-Point Arithmetic Unit"International Journal of Computer Trends and Technology (IJCTT),V4(4):751-755 April Issue 2013 .ISSN 2231-2803.www.ijcttjournal.org. Published by Seventh Sense Research Group.
Abstract: -— Floating point operations are hard to implement on Field Programmable Gate Arrays (FPGA) because of the complexity of algorithms is more. Then again, many scientific applications require floating point arithmetic because of high accuracy in their calculations. Therefore, an attempt is made to explore FPGA implementations in Institute of Electrical and Electronics Engineers (IEEE) -754 standard floating-point numbers. Many algorithms depend on floating point arithmetic because floating point representation supports huge range. In this paper an efficient implementation of an IEEE 754 single precision floating point arithmetic unit is designed in Xilinx SPARTAN 3E FPGA. VHDL environment is performed for floating point arithmetic unit design using pipelining, which provides high performance. Pipelining is used to execute multiple instructions simultaneously. In top-down design approach, four arithmetic modules, addition/ subtraction, multiplication and division are combined to form a floating point arithmetic unit. Synthesis and simulation results are obtained by using Xilinx13.1i platform.
 Yee Jern Chong and sri Parameswaram, “Configurable Multimode Embedded units floating-point for FPGAs”, IEEE Transactions on VLSI systems, pp. 2033-2044, Vol.19, No.11, November 2011.
 IEEE Standard Board and ANSI, “IEEE Standard for Binary Floating-Point Arithmetic”, IEEE Std 754.
 J. D. Bruguera and T. Lang, “Leading-One Prediction with Concurrent Position Correction”, IEEE Transactions on Computers, pp. 1083–1097, Vol. 48, No.10.
 Xilinx, http://www.xlinix/com.
 Taek-Jun Kwon, Jeff Sondeen, Jeff Draper, “Design Trade-Offs in Floating-Point Unit, Implementation for Embedded and Processing-In-Memory Systems”, USC Information Sciences Institute, 4676 Admiralty Way Marina del Rey, CA 90292 U.S.A.
 Jinwoo Suh, Dong-In Kang, and Stephen P. Crago, “Efficient Algorithms for Fixed-Point Arithmetic Operations inan Embedded PIM”, University of Southern California/Information Sciences Institute, 2005.
 Yu-Ting Pai and Yu-Kumg Chen, “The Fastest Carry Lookahead Adder”, Tutorial Report, Department of Electronic Engineering, Huafan University.
 David Narh Amanor, “Efficient Hardware Architectures for Modular Multiplication”, Communication and Media Engineering, University of Applied Sciences Offenburg, Germany, 2005.
Keywords — ALU - Arithmetic Logic Unit; Top-Down design; floating point; FPGA; Pipelined Architecture.