A New Reduced Clock Power Flip-flop for Future SOC Applications
| ||International Journal of Computer Trends and Technology (IJCTT)|| |
|© - Issue 2012 by IJCTT Journal|
|Volume-3 Issue-4 |
|Year of Publication : 2012|
|Authors :T.Kavitha , Dr.V.Sumalatha|
T.Kavitha , Dr.V.Sumalatha."A New Reduced Clock Power Flip-flop for Future SOC Applications"International Journal of Computer Trends and Technology (IJCTT),V3(4):491-495 Issue 2012 .ISSN 2231-2803.www.ijcttjournal.org. Published by Seventh Sense Research Group.
Abstract: -In this paper a novel technique is proposed based on the comparison between Conventional Conditional Data Mapping Flip-flop and Clock Pair Shared D flip flop(CPSFF) here we are checking the working of CDMFF and the conventional D Flip-flop. Due to the immense growth in nanometer technology the SOC is became the future concept of the modern electronics the number of clock transistors are also considerably increased. In this paper we propose a new system which will considerably reduce the number of transistor which will lead to the reduction in clocking power which will improve the overall power consumption.Our proposed which is designed using Pass Transistor Logic (LCPTFF) Low Power Clocked Pass Transistor Flip-Flop system is showing much better output than all other designs as mentioned in the tabulation.The simulations are done using Microwind& DSCH analysis software tools and the result between all those types are listed below.
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KeywordsFlip-flop, Low Power Clocking System, Sequential Elements, DSCH, Microwind