Design of Adder in Multiple Logic Styles for Low Power VLSI
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International Journal of Computer Trends and Technology (IJCTT) |  |
| © - Issue 2012 by IJCTT Journal | ||
| Volume-3 Issue-3 |
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| Year of Publication : 2012 | ||
| Authors :K.Venkata Siva Reddy, C.Venkataiah. |
K.Venkata Siva Reddy, C.Venkataiah."Design of Adder in Multiple Logic Styles for Low Power VLSI"International Journal of Computer Trends and Technology (IJCTT),V3(3):1068 -1073 Issue 2012 .ISSN 2231-2803.www.ijcttjournal.org. Published by Seventh Sense Research Group.
Abstract: -The main consideration for design and implementation of various logics and Arithmetic functions, such as an adder, are the choice of basic pass transistor approach due to their high operating speed and low power dissipation. The main objective of this paper is to design carry skip adder based on different technologies such as CPL (Complementary Pass Transistor Logic), DCVSPG (Differential Cascade Voltage Swing Pass Transistor Logic), SRPL (Swing Restore Pass Transistor Logic), and EEPL (Energy Economized Pass Transistor Logic). The performance of these circuits has to be compared by considering various parameters such as power consumption, delay, area, transistor count and PDP (Power Delay Product). These circuits have to be designed and simulated using DSCH3.1 and the results are to be compared with different technologies using microwind3.1.
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Keywords:Carry Skip Adder, Pass Transistor, Power Consumption, Propagation Delay.