Analysis of VoIP Traffic with Multiple Packet Transfer
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International Journal of Computer Trends and Technology (IJCTT) |  |
| © - Issue 2012 by IJCTT Journal | ||
| Volume-3 Issue-3 |
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| Year of Publication : 2012 | ||
| Authors :M.Padmaja, V.N.V. Satya Prakash. |
M.Padmaja, V.N.V. Satya Prakash."Analysis of VoIP Traffic with Multiple Packet Transfer"International Journal of Computer Trends and Technology (IJCTT),V3(3):1059 -1063 Issue 2012 .ISSN 2231-2803.www.ijcttjournal.org. Published by Seventh Sense Research Group.
Abstract: -The Low power and low energy has become an important issue in today’s consumer electronics. Any combinational circuit can be represented as a multiple inputs with single output. Multiplexers are used to design any digital combinational logic circuit. Hence it is required to design a multiplexer with low power consumption and high speed. The main objective of this paper is to design the multiplexer using complementary metal oxide semiconductor (CMOS) logic and
References-
[1] G. L .Madhumati, Dr .M .Madhavilatha and K. Ramakoteswara Rao, Power and delay analysis of a 2-to-1 multiplexer implemented in multiple logic styles for multiplexer-based decoder in Flash ADC, International Journal of Recent Trends in Engineering ,Vol 1 ,N0:4 ,2009.
[2] A.P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, (Kluwer, Norwell, MA, 1995).
[3] Jan M Rabaey, Anantha Chandrakasan, Borivoje Nikolic, Digital Integrated Circuits: A Design perspective, (2nd Edition, Prentice-Hall Inc).
[4] Neil H.E. Weste, David Harris and Ayan Banerjee, CMOS VLSI Design, A circuits and system perspective, (3rd Edition, Pearson Education, 2005).
[5] Stephen brown, Zvonko Vranesic, Fundamentals of Digital logic with VHDL design, (Tata McGraw-Hill, New Delhi, 2002).
[6] N. Ohkubo et al., A 4.4 ns CMOS 54x54-b multiplier using pass transistor multiplexer, IEEE Journal of Solid-State Circuits, vol. 30, March 1995, 251–257.
Keywords:CMOS, Low power, High Speed, Area.