Implementation and Comparative Analysis between Different Precision Interval Arithmetic based Multiplication using Modified Array Method
| ||International Journal of Computer Trends and Technology (IJCTT)|| |
|© - Issue 2012 by IJCTT Journal|
|Volume-3 Issue-2 |
|Year of Publication : 2012|
|Authors :Krutika Ranjankumar Bhagwat , Dr. Tejas V. Shah , Prof. Deepali H. Shah.|
Krutika Ranjankumar Bhagwat , Dr. Tejas V. Shah , Prof. Deepali H. Shah."Implementation and Comparative Analysis between Different Precision Interval Arithmetic based Multiplication using Modified Array Method"International Journal of Computer Trends and Technology (IJCTT),V3(2):268-273 Issue 2012 .ISSN 2231-2803.www.ijcttjournal.org. Published by Seventh Sense Research Group.
Abstract: -This paper presents the design of different precision modified array multipliers, which performs interval multiplication. Modified array multiplier requires carry save adders instead of full adders that reduces the delay in respect of conventional array multiplier. The double precision multiplication , single precision multiplication, and half precision multiplication are require 53 x 53, 24 x 24 , 11 x 11 multiplication respectively, which are done by array multiplier. Multipliers are based on interval arithmetic which provides the better accuracy, by avoiding rounding off error over conventional floating point multiplier. There is performance improvement as increasing precision, but it requires slightly more area and delay. Keywords— Double Precision, Single Precision, Half Precision , Interval Multiplication , Significand Multiplier , Array Multiplier, Modified Array Multiplier.
 Josh Milthorpe and Alistair Rendell “Learning to live with errors: A fresh look at floating-point computation”, Australian National University, Computing Conference 2005
 Gupte, ruchir “Interval arithmetic logic unit for dsp and control applications”, Electrical and Computer Engineering, Raleigh 2006
 Samir Palniker, “ Verilog HDL: A Guide to Digital Design and Synthesis”, ISBN 81-297-0092-1, @2003 SUN MICROSYSTEMS
 “ IEEE Standard 754 for Binary Floating Point Arithmetic ” , ANSI/IEEE Standard No. 754, American National Standards Institute, Washington DC , 1985.
 Behrooz Parhami , “Computer Arithmetic, Algorithms and Hardware Designs” , 2nd Edn, OXFORD, Mar. 2011
 Alexandru Amaricai Mircea Vladuaiu Lucian Prodan Mihai Udrescu Oana Boncalo “Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor”, Computer Science and Engineering Department, ©2007 IEEE
 Michael J. Schulte and Earl E. Swartzlander Jr., “A Performance Comparison Study on Multiplier Designs” ,IEEE Transaction On Computers, May 2000
 Yong Dou S. Vassiliadis G. K. Kuzmanov G. N. Gaydadjiev , “64-bit Floating-Point FPGA Matrix Multiplication” , National Laboratory for Computer Engineering, FPGA’05, Monterey, California, USA, February , 2005
 Anane Nadjia, Anane Mohamed, Bessalah Hamid, Issad Mohamed & Messaoudi khadidja, “Hardware Algorithm for Variable Precision Multiplication on FPGA” © 2009 IEEE
 James E. Stine and Michael J. Schulte “A Combined Interval and Floating Point Multiplier”, Computer Architecture and Arithmetic Laboratory ,Electrical Engineering and Computer Science Department, Lehigh University, Bethlehem, PA 18015
 Sparc Architecture Manual
 Prof. LohCS3220- Processor Design “Carry-Save Addition” - Spring 2005, February , 2005
 “Carry Save Adder Trees in Multipliers” ecen 6 2 6 3 advanced vl sI design november 3, 1999
 .N. Marimuthu1, P. Thangaraj “Low Power High Performance Multiplier”, Anna University, Tamil nadu , India
 Steve Kilts, “Advanced FPGA Design Architecture, Implementation, and Optimization”, Wiley – Interscience, A John Wiley & Sons, ISBN 978-0-470-05437-6, @ 2007 IEEE.
Keywords —: SHA-3, JH , BLAKE , Hash, Compression Function.