A Re-router for Reducing Wire Length in Multi- Layer No-Dogleg Channel Routing

International Journal of Computer Trends and Technology (IJCTT)          
© 2016 by IJCTT Journal
Volume-38 Number-2
Year of Publication : 2016
Authors : Swagata Saha Sau, Rajat Kumar Pal
DOI :  10.14445/22312803/IJCTT-V38P120


Swagata Saha Sau, Rajat Kumar Pal "A Re-router for Reducing Wire Length in Multi- Layer No-Dogleg Channel Routing". International Journal of Computer Trends and Technology (IJCTT) V38(2):110-118, August 2016. ISSN:2231-2803. www.ijcttjournal.org. Published by Seventh Sense Research Group.

Abstract -
The minimization of total wire length is one of the most key issue in VLSI physical design automation, as it reduces the cost of physical wiring required along with the electrical hazards of having long wires in the interconnection, power consumption, and signal propagation delay. So, it is still important as cost as well as high performance issue. The problem of reduced wire length routing solutions in no-dogleg reserved two-layer (VH) and multi-layer (ViHi, 2 ? i < dmax and ViHi+1, 2 ? i < dmax ? 1) channel routing is NP-hard, so, it is interesting to develop heuristic algorithms that compute routing solutions of as minimum total (vertical) wire length as possible. Here we propose two algorithms to reduce the total (vertical) wire length in channel routing problem. First we develop an efficient re-router Further_Reduced_Wire_Length (FRWL) to optimize the wire length in the reserved two-layer (VH) no-dogleg channel routing model and then we develop an algorithm Multi-Layer_Reduced_Wire_Length (MLRWL) to minimize the total (vertical) wire length in channel routing problem in the reserved multi-layer (ViHi, 2 ? i < dmax and ViHi+1, 2 ? i < dmax ? 1) no-dogleg Manhattan routing models, where vertical and horizontal layers of interconnect alternate. Experimental results computed for available benchmark instances indicate that the algorithms perform well.

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Channel routing problem, Manhattan routing, No-dogleg, Parametric difference, Wire length minimization, VLSI.