Fault Detection and Test Minimization Methods for Combinational Circuits - A Survey
| ||International Journal of Computer Trends and Technology (IJCTT)|| |
|© - Issue 2011 by IJCTT Journal|
|Volume-2 Issue-2 |
|Year of Publication : 2011|
|Authors :SM. Thamarai , Dr K.Kuppusamy, Dr T.Meyyappan.|
SM. Thamarai , Dr K.Kuppusamy, Dr T.Meyyappan. "Fault Detection and Test Minimization Methods for Combinational Circuits - A Survey"International Journal of Computer Trends and Technology (IJCTT),V2(2):622-628 Issue 2011 .ISSN 2231-2803.www.ijcttjournal.org. Published by Seventh Sense Research Group.
Abstract: - Rapid increase in population increased the usage of digital components dramatically and their production. For profitable income, the cost of the finished product and time taken for marketing the product needs to be reduced. In this paper, the authors conducted extensive survey of methods developed earlier to detect faults and minimize test set in digital circuits. The survey is limited to methods for simple combinational circuits only. In effect, this paper compares 11 different fault detection and test minimization methods for simple circuits. In addition, a survey on evolutionary techniques for optimizing the test set in digital circuits is performed. The surveyed methods are widely accepted by industries manufacturing digital circuits. A very brief introduction to entire flow of test minimization process is also presented.
 Alok Shreekant Doshi, “Independence Fault Collapsing and Concurrent Test Generation”, MSc Thesis,Auburn university , Alabama, May 11, 2006.  V. Amar and N. Condulmari, "Diagnosis of large combinational networks," IEEE Trans. Electronic Computers, vol. EC-16, pp. 675-680, October 1967.  D. B. Armstrong, "On finding a nearly minimal set of fault detection tests for combinational logic nets," IEEE Trans. Electron. Comput., vol. EC-15, Feb. 1966, pp. 66-73.  L. W. Bearnson, "Arithmetic error detection in digital computer," M.S. thesis, Dept. of Elec. Engrg., Syracuse University,Syracuse, N. Y., May 1965.  L.W.Bearnson and C.C.Carroll, “On the design of minimum length fault tests for combinational circuits”, IEEE Trans. Computers, vol.C-20, No. 11, 1971, pp. 1353-1356.  G. Boole, A Treatise on the Calculus of Finite Difference. New York: Dover (republication of 1872 edition by MacMillan and Co., London).  Kalyana R. Kantipudi,”Minimizing N-Detect Tests for Combinational Circuits”, M.SC Thesis,Auburn University, Auburn, Alabama ,May 10, 2007.  W. H. Kautz, "Fault testing and diagnosis in combinational digital circuits," IEEE Trans. Comput., vol. C-17, pp. 352-366, Apr. 1968.  Z.Kohavi and D.A.Spires, “Designing sets of fault detection tests for combinational logic circuits”, IEEE Trans. Computers, vol. C-20, No. 12, 1971, pp 1463-1469
Keywords— Combinational Circuits, Fault Detection, Genetic Algorithm, ILP, Stuck-at-faults, Test Minimization.