Low Power testing by don’t care bit filling technique.
| ||International Journal of Computer Trends and Technology (IJCTT)|| |
|© - Sep to Oct Issue 2011 by IJCTT Journal|
|Volume-1 Issue-2 |
|Year of Publication : 2011|
|Authors :Chetan Sharma.|
Chetan Sharma. "Low Power testing by don’t care bit filling technique"International Journal of Computer Trends and Technology (IJCTT),V2(2):314-316 Sep to Oct Issue 2011 .ISSN 2231-2803.www.ijcttjournal.org. Published by Seventh Sense Research Group.
Abstract: Test power is major issue of recent scenario of VLSI testing. There are many test pattern generation techniques for testing of combinational circuits with different tradeoffs. The don’t care bit filling method can be used for effective test data compression as well as reduction in scan power. This paper gives a new advancement in automatic test pattern generation method by feeling don’t care bit of the test vector to optimize the switching activities. Finally this concept produces low power testing.
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KeywordsATPG test vector generation, Huffman code, Parity bit generation, Switching activity.