Efficient Layout Design of 4-Bit Full Adder using Transmission Gate
||International Journal of Computer Trends and Technology (IJCTT)||
|© 2015 by IJCTT Journal|
|Year of Publication : 2015|
|Authors : Anurag Yadav, Rajesh Mehra|
|DOI : 10.14445/22312803/IJCTT-V23P125|
Anurag Yadav, Rajesh Mehra "Efficient Layout Design of 4-Bit Full Adder using Transmission Gate". International Journal of Computer Trends and Technology (IJCTT) V23(3):116-119, May 2015. ISSN:2231-2803. www.ijcttjournal.org. Published by Seventh Sense Research Group.
In any digital circuit surface area and power both are very important parameters. In this paper 4- bit full adder using transmission gate is designed. To design 4- bit full adder two methods are used. First is semi custom design method and second is full custom design method. In first semi custom design method a layout of 4-bit full adder is designed with available width and length of the transistor. In full custom design method create a layout with the help of reduced width of transistor. 4-bit full adder has one important element which is full adder. Full adder is designed based upon transmission gate. Transmission gate is used to improve the logic level of signal. 90nm technology is used to simulate these two design methods. It can be found from the simulated results that full custom design layout results in 29.65% reduction of surface area of 4-bit full adder as compared to semi custom design. It can also be observed from the simulated results that full custom layout results in 26.22% reduction of power as compared to semi custom design.
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ADDER, MICROWIND, TRANSMISSION GATE, VLSI