Design and Analysis of On-Chip Router for Network On Chip
| ||International Journal of Computer Trends and Technology (IJCTT)|| |
|© July to Aug Issue 2011 by IJCTT Journal|
|Volume-1 Issue-3 |
|Year of Publication : 2011|
|Authors : Ms. A.S. Kale,Prof. M.A.Gaikwad.|
Ms. A.S. Kale,Prof. M.A.Gaikwad. "Design and Analysis of On-Chip Router for Network On Chip"International Journal of Computer Trends and Technology (IJCTT),V1(3):264-268 July to Aug Issue 2011 .ISSN 2231-2803.www.ijcttjournal.org. Published by Seventh Sense Research Group.
Abstract: —Continuous scaling of CMOS technology makes it possible to integrate a large number of heterogeneous devices that need to communicate efficiently on a single chip. For this efficient routers are needed to takes place communication between these devices. This paper gives the design of on-chip routers based on optimizing power consumption and chip area. Proposed architecture of on-chip router in this paper give the results in which power consumption is reduced and silicon area is also minimize.
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KeywordsArbiter, Network on chip (NOC), Router.