Real-Time Object Detection and Recognition in FPGA-Based Autonomous Driving Systems

  IJCTT-book-cover
 
         
 
© 2024 by IJCTT Journal
Volume-72 Issue-4
Year of Publication : 2024
Authors : Muthukumaran Vaithianathan
DOI :  10.14445/22312803/IJCTT-V72I4P119

How to Cite?

Muthukumaran Vaithianathan, "Real-Time Object Detection and Recognition in FPGA-Based Autonomous Driving Systems," International Journal of Computer Trends and Technology, vol. 72, no. 4, pp. 145-152, 2024. Crossref, https://doi.org/10.14445/22312803/IJCTT-V72I4P119

Abstract
This research paper presents an innovative methodology for the identification and detection of objects in autonomous driving systems that employ field-programmable gate arrays (FPGAs). Through the integration of deep learning methodologies with FPGA hardware acceleration, the approach successfully attains the minimal latency and optimal precision necessary for secure navigation. By conducting data acquisition, preprocessing, and model training, this can refine the system's performance. By employing parallel computing and hardware optimisation techniques, the FPGA implementation achieves these objectives. Based on experimental data, the FPGA-based approach outperforms conventional CPU and GPU implementations in terms of power efficiency, inference latency, and detection precision. The widespread adoption of field-programmable gate arrays (FPGAs) for enhanced object recognition and identification in autonomous vehicles is imminent due to their exceptional compatibility with autonomous driving systems.

Keywords
Real-Time Object Detection, Object Recognition, Field Programmable Gate Array, Deep Learning, Autonomous Driving.

Reference

[1] Bilal Jan et al., “Designing a Smart Transportation System: An Internet of Things and Big Data Approach,” IEEE Wireless Communications, vol. 26, no. 4, pp. 73-79, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[2] Longyin Wen et al., UA-DETRAC: A New Benchmark and Protocol for Multi-Object Detection and Tracking,” Computer Vision and Image Understanding, vol. 193, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[3] Zhuang Liu et al., “Learning Efficient Convolutional Networks through Network Slimming,” 2017 IEEE International Conference on Computer Vision, Venice, Italy, pp. 2755-2763, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[4] S. Navaneethan et al., “Image Display Using FPGA with BRAM and VGA Interface for Multimedia Applications,” 2023 8th International Conference on Communication and Electronics Systems, Coimbatore, India, pp. 77-83, 2023.
[CrossRef] [Google Scholar] [Publisher Link]
[5] Yufei Ma et al., “Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks,” Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, pp. 45- 54, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[6] Joseph Redmon, and Ali Farhadi, “YOLO9000: Better, Faster, Stronger,” 2017 IEEE Conference on Computer Vision and Pattern Recognition, Honolulu, HI, USA, pp. 6517-6525, 2017.
[CrossRef] [Google Scholar] [Publisher Link]
[7] Srigitha S. Nath, “SD Card Interface Using FPGA for Multimedia Applications,” 2022 6th International Conference on Electronics, Communication and Aerospace Technology, Coimbatore, India, pp. 388-394, 2022.
[CrossRef] [Google Scholar] [Publisher Link]
[8] Zixiao Wang et al., “Sparse-YOLO: Hardware/Software Co-Design of an FPGA Accelerator for YOLOv2,” IEEE Access, vol. 8, pp. 116569-116585, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[9] Seul-Ki Yeom et al., “Pruning by Explaining: A Novel Criterion for Deep Neural Network Pruning,” Pattern Recognition, vol. 115, pp. 1-14, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[10] Chen Chen et al., “A PYNQ-Compliant Online Platform for Zynq-Based DNN Developers,” Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside CA USA, pp. 1-185, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[11] S.P. Kaarmukilan, Soumyajit Poddar, and K. Amal Thomas, “FPGA Based Deep Learning Models for Object Detection and Recognition Comparison of Object Detection Comparison of Object Detection Models Using FPGA,” 2020 Fourth International Conference on Computing Methodologies and Communication, Erode, India, pp. 471-474, 2020.
[CrossRef] [Google Scholar] [Publisher Link]
[12] Edward Rzaev, Anton Khanaev, and Aleksandr Amerikanov, “Neural Network for Real-Time Object Detection on FPGA,” 2021 International Conference on Industrial Engineering, Applications and Manufacturing, Sochi, Russia, pp. 719-723, 2021.
[CrossRef] [Google Scholar] [Publisher Link]
[13] V. Yusuf Çambay et al., “Object Detection on FPGAs and GPUs by Using Accelerated Deep Learning,” 2019 International Artificial Intelligence and Data Processing Symposium, Malatya, Turkey, pp. 1-5, 2019.
[CrossRef] [Google Scholar] [Publisher Link]
[14] Dezheng Zhang et al., “End-to-End Acceleration of the YOLO Object Detection Framework on FPGA-Only Devices,” Neural Computing and Applications, vol. 36, pp. 1067-1089, 2024.
[CrossRef] [Google Scholar] [Publisher Link]
[15] Jiaqi Zhai et al., “FPGA-Based Vehicle Detection and Tracking Accelerator,” Sensors, vol. 23, no. 4, pp. 1-26, 2023.
[CrossRef] [Google Scholar] [Publisher Link]