Adiabatic Logic For Low Power Application Using Design 180nm Technology

International Journal of Computer Trends and Technology (IJCTT)          
© - April Issue 2013 by IJCTT Journal
Volume-4 Issue-4                           
Year of Publication : 2013
Authors : Nikunj R Patel, Sarman K Hadia


Nikunj R Patel, Sarman K Hadia "Adiabatic Logic For Low Power Application Using Design 180nm Technology"International Journal of Computer Trends and Technology (IJCTT),V4(4):800-804 April Issue 2013 .ISSN Published by Seventh Sense Research Group.

Abstract: -Adiabatic circuits and standard CMOS logic are widely employed in Low power VLSI chips to achieve high system performance. The power saving of adiabatic circuit can reach more than 90% compared to conventional static CMOS logic. The clocking schemes and signal waveforms of adiabatic are different from those of standard CMOS circuits. This thesis work demonstrates the low power dissipation of Adiabatic Logic by presenting the results of designing various design/ cell units employing Adiabatic Logic circuit techniques( an inverter, a two-input NAND gate, a two-input NOR gate, a two-input XOR gate, a two-to-one multiplexer and a one-bit carry Adder) This paper also investigates the different power delay product over the wide range of supply voltages. Power dissipation has been calculated for different values.



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Keywords — Low Power, Adiabatic logic, Energy dissipation, Positive Feedback Adiabatic Logic, Energy recovery