Design and Analysis of On-Chip Router for Network On Chip
 | International Journal of Computer Trends and Technology (IJCTT) |  |
| © July to Aug Issue 2011 by IJCTT Journal | ||
| Volume-1 Issue-3 | ||
| Year of Publication : 2011 | ||
| Authors : Ms. A.S. Kale,Prof. M.A.Gaikwad. |
Ms. A.S. Kale,Prof. M.A.Gaikwad. "Design and Analysis of On-Chip Router for Network On Chip"International Journal of Computer Trends and Technology (IJCTT),V1(3):264-268 July to Aug Issue 2011 .ISSN 2231-2803.www.ijcttjournal.org. Published by Seventh Sense Research Group.
Abstract: —Continuous scaling of CMOS technology makes it possible to integrate a large number of heterogeneous devices that need to communicate efficiently on a single chip. For this efficient routers are needed to takes place communication between these devices. This paper gives the design of on-chip routers based on optimizing power consumption and chip area. Proposed architecture of on-chip router in this paper give the results in which power consumption is reduced and silicon area is also minimize.
References-
[1] W. 1. Dally and B. Towles, Route Packets, Not Wires: On-Chip Interconnection Networks, In Proceedings of the 38th Design Automation Conference, p.684 (2001) [2] L. Benini and D. Micheli, Networks on Chips: A New SoC Paradigm, IEEE Computer, 35, p.70 (2002) [3]Khalid Latif, Tiberiu Seceleanu, Hannu Tenhunen, Power and Area Efficient Design of Network-on-Chip Router Through Utilization of Idle Buffers. [4]Eung S. Shin, Vincent J. Mooney III and George F. Riley, Round-robin Arbiter Design and Generation
KeywordsArbiter, Network on chip (NOC), Router.