Clock Branch Shearing Flip Flop Based on Signal Feed Through Technique

  IJCTT-book-cover
 
International Journal of Computer Trends and Technology (IJCTT)          
 
© 2016 by IJCTT Journal
Volume-39 Number-3
Year of Publication : 2016
Authors : Pragati Gupta, Dr. Rajesh Mehra
  10.14445/22312803/IJCTT-V39P121

MLA

Pragati Gupta, Dr. Rajesh Mehra "Clock Branch Shearing Flip Flop Based on Signal Feed Through Technique". International Journal of Computer Trends and Technology (IJCTT) V39(3):123-128, September 2016. ISSN:2231-2803. www.ijcttjournal.org. Published by Seventh Sense Research Group.

Abstract -
Flip-flops are used to store state information in all types of controlling units of integrated circuits. The efficiency of synchronous circuits depends on the performance of flip-flop. To calculate the performance of flip-flop power and delay is the two most important factors. To reduce the power consumption and delay of flip -flop, signal feed through scheme is used in this paper. As in this scheme signal is directly driven the internal node of the latch, so the speed of the circuit is improved. In this paper the designing of explicit type pulse trigger flip-flop on CMOS 90nm technology is proposed. Double edge triggering is also used in this paper to improve power and delay. When compared to the existing design this paper gives improved delay, so the speed of the circuit is also improved.

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Keywords
Flip-flop, Low power electronics, power dissipation and VLSI