Efficient VLSI Architecture for 1-D 9/7 Discrete Wavelet Transform

  IJCTT-book-cover
 
International Journal of Computer Trends and Technology (IJCTT)          
 
© 2016 by IJCTT Journal
Volume-38 Number-1
Year of Publication : 2016
Authors : Meenakshi kuwade, Rakesh mandliay
  10.14445/22312803/IJCTT-V38P103

MLA

Meenakshi kuwade, Rakesh mandliay "Efficient VLSI Architecture for 1-D 9/7 Discrete Wavelet Transform". International Journal of Computer Trends and Technology (IJCTT) V38(1):15-18, August 2016. ISSN:2231-2803. www.ijcttjournal.org. Published by Seventh Sense Research Group.

Abstract -
Conventional distributed arithmetic (DA) is popular in field programmable gate array (FPGA) design, and it features on-chip ROM to achieve high speed and regularity. In this paper, we describe high speed area efficient 1-D discrete wavelet transform (DWT) using 9/7 filter based new efficient distributed arithmetic (NEDA) Technique. Being area efficient architecture free of ROM, multiplication, and subtraction, NEDA can also expose the redundancy existing in the adder array consisting of entries of 0 and 1. This architecture supports any size of image pixel value and any level of decomposition. The parallel structure has 100% hardware utilization efficiency.

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Keywords
1-D Discrete Wavelet Transform (DWT), NEDA, Low Pass Filter, High Pass Filter, Xilinx Simulation.