Design and Analysis of Multiplier Accumulation Unit by using Hybrid Adder

  IJCTT-book-cover
 
International Journal of Computer Trends and Technology (IJCTT)          
 
© 2016 by IJCTT Journal
Volume-37 Number-2
Year of Publication : 2016
Authors : Amiya Prakash, Dr. Kanika Sharma
  10.14445/22312803/IJCTT-V37P118

MLA

Amiya Prakash, Dr. Kanika Sharma "Design and Analysis of Multiplier Accumulation Unit by using Hybrid Adder". International Journal of Computer Trends and Technology (IJCTT) V37(2):96-102, July 2016. ISSN:2231-2803. www.ijcttjournal.org. Published by Seventh Sense Research Group.

Abstract -
A new architecture of Multiplier accumulation unit (MAC) by using reversible logic gates Algorithm for reducing circuit complexity, power consumption and delays, have been proposed and implemented on Xilinx FPGA device. By combining a reversible multiplier and reversible adder, design a hybrid type Multiplier accumulation unit by using reversible logic gates. The reversible logic gate algorithm will reduce the garbage bits and logical components during arithmetic manipulations. Fast adders and multipliers are the essential part of the digital signal processing system. The speed of multiplier and adder operation is of great importance in digital signal processing as well as area is also great importance to design a MAC unit in digital signal processing. The proposed algorithm maximally decreases function complexity during synthesis steps.

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Keywords
Reversible logic gates; hybrid adders; multipliers and accumulator.