Design of a Low Power and Stable 11T SRAM cell with bit-interleaving capability

International Journal of Computer Trends and Technology (IJCTT)          
© 2016 by IJCTT Journal
Volume-37 Number-2
Year of Publication : 2016
Authors : Shivendra Kumar Sharma, Bhavana P.Shrivastava


Shivendra Kumar Sharma, Bhavana P.Shrivastava "Design of a Low Power and Stable 11T SRAM cell with bit-interleaving capability". International Journal of Computer Trends and Technology (IJCTT) V37(2):67-72, July 2016. ISSN:2231-2803. Published by Seventh Sense Research Group.

Abstract -
A low power and high stable single ended 11T SRAM cell has been proposed with bit interleaving capability. A column aware scheme is used in the cell to achieve highly stable SRAM cell which exhibit better performance than the previous designs. The proposed design has robust read operation and exhibits lower power consumption and better stability as compared to existing designs. This proposed 11T SRAM has been compared with conventional 6T SRAM cell and 9T SRAM cell in term of Power consumption, Delay and Power Delay Product (PDP) at various supply voltages as 1.8V, 1.6V and 1.4V. For the stability analysis SNM (Static Noise Margin) also analyzed at the supply voltage 1.8V. The simulations of all circuits are done on Cadence Virtuoso at 180nm CMOS technology and the simulation results are analyzed and verify to show that proposed design is better than the existing designs. The proposed 11T SRAM shows the better performances in terms of power consumption and PDP at all the supply voltages. At 1.8V power saving by the proposed design is 73.88% and improvement in PDP is 71.53% compared to standard 6T SRAM cell and significant improvement is observed at other supply voltages also. In term of stability the proposed design showing good result as compare to existing designs.

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SRAM cell, Leakage Power, Low Power, Stability, Bit-interleaving, PDP.