Design of a Low Power and Stable 11T SRAM cell with bit-interleaving capability

  IJCTT-book-cover
 
International Journal of Computer Trends and Technology (IJCTT)          
 
© 2016 by IJCTT Journal
Volume-37 Number-2
Year of Publication : 2016
Authors : Shivendra Kumar Sharma, Bhavana P.Shrivastava
  10.14445/22312803/IJCTT-V37P114

MLA

Shivendra Kumar Sharma, Bhavana P.Shrivastava "Design of a Low Power and Stable 11T SRAM cell with bit-interleaving capability". International Journal of Computer Trends and Technology (IJCTT) V37(2):67-72, July 2016. ISSN:2231-2803. www.ijcttjournal.org. Published by Seventh Sense Research Group.

Abstract -
A low power and high stable single ended 11T SRAM cell has been proposed with bit interleaving capability. A column aware scheme is used in the cell to achieve highly stable SRAM cell which exhibit better performance than the previous designs. The proposed design has robust read operation and exhibits lower power consumption and better stability as compared to existing designs. This proposed 11T SRAM has been compared with conventional 6T SRAM cell and 9T SRAM cell in term of Power consumption, Delay and Power Delay Product (PDP) at various supply voltages as 1.8V, 1.6V and 1.4V. For the stability analysis SNM (Static Noise Margin) also analyzed at the supply voltage 1.8V. The simulations of all circuits are done on Cadence Virtuoso at 180nm CMOS technology and the simulation results are analyzed and verify to show that proposed design is better than the existing designs. The proposed 11T SRAM shows the better performances in terms of power consumption and PDP at all the supply voltages. At 1.8V power saving by the proposed design is 73.88% and improvement in PDP is 71.53% compared to standard 6T SRAM cell and significant improvement is observed at other supply voltages also. In term of stability the proposed design showing good result as compare to existing designs.

References
[1] W. R. E. Aly and M. A. Bayoumi, "Low-power cache design using 7T SRAM cell ", IEEE Trans. Circ. Sys. , vol. 54, no. 4,pp. 318-322, April 2007.
[2] S. A. Tawfik and V. Kursun, "Low power and roubst 7T dual- Vt SRAM circuit", in Proc. IEEE Int. Symp. Circ. Sys. , ISCAS 2008, Seatle, W A, USA, 2008, pp. 1452-1455.
[3] B.H. Calhoun, J.F. Ryan, S. Khanna, et al., “Flexible circuits and architectures for ultralow power”, Proc. IEEE , 2010 , vol. 98 , pp. 267–282.
[4] Ik Joon Chang, Jae-Joon Kim, et al., “A 32 kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS”, IEEE J. Solid-State Circuits vol. 44 , no. 2 , pp. 650–658 , Feb. 2009.
[5] Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsan, et al., “A single-ended disturbfree 9T subthreshold SRAM with cross-point data-aware write word-line structure, negative bit-line, and adaptive read operation timing tracing”, IEEE J. Solid-State Circuits vol. 47, no. 6 , pp. 1–14, June 2012.
[6] Meng-Fan Chang, Shi-Wei Chang, Po-Wei Chou, et al., “A 130 mV SRAM with expanded write and read margins for subthreshold applications”, IEEE J. Solid-State Circuits vol. 46 , no.2, pp. 520–529 , Feb. 2011.
[7] Ming-Hung Chang, Yi-Te Chiu, Wei Hwang, et al., “Design and Iso-area vmin analysis of 9T subthreshold SRAM with bitinterleaving scheme in 65-nm CMOS”, IEEE Trans. Circuits Syst.—II: vol. 59 , no.7 , pp. 429–433 , July 2012.
[8] Anh-Tuan Do, Jeremy Yung Shern Low, Joshua Yung Lih Low, et al., “An 8T differential SRAM with improved noise margin for bit-interleaving in 65 nm CMOS,” IEEE Trans. Circuits Syst.—I Regul.vol. 58, no. 6, pp. 1252–1263, June 2011.
[9] S. Hanson, B. Zhai, K. Bernstein, et al., “Ultralow-voltage, minimum-energy CMOS”, IBM J. Res. Develop ,vol.50 , pp. 469– 490 , 2006.
[10] E. Seevinck et al., “Static-noise margin analysis of MOS SRAM cells,” IEEE J. Solid-State Circuits, vol. SC-22, no. 2, pp. 748–754, May 1987.
[11] Koichi Takeda, Yasuhiko Hagihara, Yoshiharu Aimoto, et al., “A read-static noise-margin-free SRAM cell for low-VDD and high-speed applications”, IEEE J.Solid-State Circuits, vol. 41, no.1, pp. 113-121, Jan. 2006.
[12] Liang Wen , Zhikui Duan , Yi Li , Xiaoyang Zeng , “Analysis of a read disturb-free 9T SRAM cell with bitinterleaving capability” , Microelectronics Journal , vol. 45, pp. 815–824, mar. 2014.
[13] K. khare, R. Kar, D. Mandal, S.P. Ghosal, “Analysis of leakage current and leakage power reduction during write operation in CMOS SRAM cell” IEEE international conference on communication and signal processing, April 2014, pp. 523- 527.
[14] J. Singh, 1. Mathew, and K. D. Pradhan, "A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies", in Proc. IEEE Int. SOC Conf. SOCC, 2008 , pp. 243-246.
[15] P. Hazucha, T. Karnik, and J. Maiz, et al., “Neutron soft error rate measurement in 90-nm CMOS process and scaling trends in SRAM from 0.25-um to 90-nm generation”, in: Proc. 2003 IEDM Technical Digest, 2003, pp. 21.5.1– 21.5.4.

Keywords
SRAM cell, Leakage Power, Low Power, Stability, Bit-interleaving, PDP.