Analysis of Word length Effect in Fir Filter

International Journal of Computer Trends and Technology (IJCTT)          
© 2015 by IJCTT Journal
Volume-30 Number-2
Year of Publication : 2015
Authors : Er.Sheenu Rana, Er.Ranbirjeet Kaur, Rajesh Mehra


Er.Sheenu Rana, Er.Ranbirjeet Kaur, Rajesh Mehra "Analysis of Word length Effect in Fir Filter". International Journal of Computer Trends and Technology (IJCTT) V30(2):104-107, December 2015. ISSN:2231-2803. Published by Seventh Sense Research Group.

Abstract -
This paper presents design and simulation of FIR filter for fixed point. Three different input precision bits are used for design simulation namely 8 bit, 16 bit and 32 bit. The design has been analyzed and compared in terms of accuracy and less stop band attenuation. The hardware requirement is also computed in terms of multipliers and adders. It can be observed from result that using more no of bits gives more accurate output signal. Multiplier and adders requirement will remain same if order is fixed f or all 8, 16 and 32 bit input signal.

[1]Andrew G. Demister , Malcon D. Macleod,”Comparision Of Fixed Point FIR Digital Filter Techniques”,” IEEE Transaction on circuits and system II analog and digital signal processing”Vol 44,pp-312- 319,No 7, July 1997
[2.]Chia–Yuyao,Wei-ChuHsia,Yung-Hsiangho,”Designing Hardware –Efficient Fixed Point FIR Filters in an Expanding Subexpression space”,”IEEE transaction on circuits and syatem- I”Vol.61,pp 212-216,No. 1,January2014.
[3]Aparna Tiwari, Vandana Thakre, Karuna Markam, “Performance Analysis of FIR Digital High Pass Filters”, International Journal of Computer & Communication Engineering Research, Vol. 2, pp. 89-92, 2 March 2014.
[4] Manish Trika, Rajesh Mehra, “BER and Cost Analysis of FIR filter For digital Transmission System”, International Journal Of Industrial Elctronic and electrical engineering, Vol. 2,Issue 9,September 2014
[5].Jean –Jacques vandenbussche,peter lee,joan peutemen “Multiplicative finite impulse response filters:implementations and application using field programmable gate arrays”,”IET journal of signal processing”,Vol. 9 ,ISS. 5,pp 449-556,16th February 2015.
[6].Arushi Garg ,Rajesh mehra ,”Design analysis of high pass filter using different techniques”,International journal of Advance Research in science and engineering IJARSE”,Vol.3,pp 144- 151,September 2014.
[7].Rajesh mehra,Sawapna Devi,”FPGA based design of high performance Decimator using DA LUT algo” “ACEEE International Journal on Signal and Image Processing”,Vol.1,pp-9- 13,issue 2,2010.
[8] Rajesh mehra,Lajwant singh,”Cost analysis and simulation of decimator for multirate application” “International journal of computer and electronics engineering ”,Vol.1,pp-212-219,issue 2,2010.
[9].Kanu priya and Rajesh mehra .”Area efficient design of FIR filter using symmetric Structure.” International Journal of Advanced research in computer and communication Engineering, Vol.1,Issue 10,pp.122-129,2012.

FIR , Word length, Fixed point ,Floating Point, Quantization, Direct firm I, High pass filter.