Enhancement of SR Flip Flop Layout Design in 45nm Technology

  IJCTT-book-cover
 
International Journal of Computer Trends and Technology (IJCTT)          
 
© 2015 by IJCTT Journal
Volume-25 Number-3
Year of Publication : 2015
Authors : Avneet Kaur, Rajesh Mehra
  10.14445/22312803/IJCTT-V25P123

MLA

Avneet Kaur, Rajesh Mehra "Enhancement of SR Flip Flop Layout Design in 45nm Technology". International Journal of Computer Trends and Technology (IJCTT) V25(3):118-122, July 2015. ISSN:2231-2803. www.ijcttjournal.org. Published by Seventh Sense Research Group.

Abstract -
This paper examines three different flip flop layouts in performance. The flip flop designs are implemented in a layout level which develops an optimized design using recent CMOS layout tools. All the flip flop layouts have been designed and simulated in 45nm technology. After that, a parametric analysis has been done. In this paper, an SR flip flop has been developed using full automatic design flow, semicustom design flow and full custom design flow. The performance of SR flip flop layouts using different design flows has been analyzed and compared in terms of area, delay and power consumption. The simulation results show that the area occupied by SR flip flop implemented using full custom design flow improved by 30% and power consumption gets reduced by 46.4% in comparison to the semi-custom design. Also, the area occupied by SR flip flop in full custom design improved by 62.7% and power consumption reduced by 67.1% in comparison to the full automatic design.

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Keywords
CMOS integrated circuits, CMOS technology, Design methodology, Latches, Flip flops.