Power and Area analysis of Flip Flop using different techniques

  IJCTT-book-cover
 
International Journal of Computer Trends and Technology (IJCTT)          
 
© 2015 by IJCTT Journal
Volume-24 Number-2
Year of Publication : 2015
Authors : Neha Thapa , Dr. Rajesh Mehra
  10.14445/22312803/IJCTT-V24P112

MLA

Neha Thapa, Dr. Rajesh Mehra "Power and Area analysis of Flip Flop using different techniques". International Journal of Computer Trends and Technology (IJCTT) V24(2):57-62, June 2015. ISSN:2231-2803. www.ijcttjournal.org. Published by Seventh Sense Research Group.

Abstract -
The use of very large scale Integration (VLSI) technology in high performance computing, wireless communication and consumer electronics has been rising at a very fast rate. The challenge of advanced VLSI technology is growing in leakage power consumption. In these days standby leakage power dissipation is emerging as the major design consideration. Leakage control is very important, especially for low power applications and handheld devices such as cellular phones and PDA. This paper enumerates a low power and area of proposed pass transistor based flip flop using self adjustable voltage level circuit by comparison with different CMOS techniques. This work analysis the power and area of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. All the circuits are simulated with and without application of leakage reduction techniques. The circuits are simulated with CMOS in MICROWIND and DSCH using 180nm technology.

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Keywords
CMOS, Leakage Power, Pass Transistors, Process Technology, Stacking Effect, Transmission Gates